Design of Two 28 GHz Doherty Power Amplifier Topologies with Vertical In(Ga)As Nanowire Transistors

Abstract: In this Master’s thesis, two different 28 GHz Doherty power amplifiers (DPAs) are designed, for high power added efficiency (PAE), in the common source (CS) and cascoded topology respectively. The results are analyzed and compared between the two approaches. The DPAs are designed using AWR design environment with virtual source (VS) models of In(Ga)As nanowire transistors and 50 nm gate length. The CS topology achieves a simulated gain of 9.9 dB, a saturated output power (Psat) of 19.7 dBm, and 3-dB bandwidth (BW3dB) from 25.5 to 31.1 GHz. The PAE at 6-dB power back-off (PBO) and PAE at 9-dB PBO are 21.2 % and 15.5 %, respectively. Simulations with a 64-QAM signal were performed. For the highest allowed error vector magnitude, EVM = 5.5 %, output power of 14.8 dBm and a PAE of 23.3 % was achieved. The cascoded topology achieves a gain of 10.6 dBm, Psat of 21.2 dBm and a BW3dB from 26.0 to 30.3 GHz. The PAE at 6-dB PBO and 9-dB PBO is 21.1 % and 15.9 %, respectively. For the highest allowed EVM, output power of 17.1 dBm and a PAE of 24.5% was achieved.