Filter Design for an HVDC protection IED

Abstract: A selective fault detection approach is necessary for successful implementation of multi-terminal high-voltage direct-current (HVDC) grids. Fault detection is per- formed by an intelligent electronic device (IED) that takes in voltage and current measurements, performs fault detection algorithms, and outputs, e.g., trip signals for circuit breakers. A digital low-pass filter is utilised for removing the noise from the signal monitored. The amount of delay imposed on the signal by the filter implementation is critical for speed requirements of DC fault detection. The goal of this research is selecting the best performing design of a digital filter based on considerations, which are application-specific. After considering the theoretical constraints and previous research conducted, a filter design most suitable for the fault detection in HVDC grids is proposed. A series of specifications of Butter- worth filters are tested in a lab environment using the intelligent electronic device (IED) prototype and the dv/dt fault detection algorithm. The behaviour of the filter is studied with respect to changes in threshold setting and slope of a voltage collapse. The speed and accuracy of fault detection are the criteria used for as- sessment of filter performance. The suggested filter design improves the accuracy of fault detection to 2.5 % as compared to 8 % when using no filter (both — for the lowest dv/dt threshold setting). The improved filter shows a more consistent performance across the operational range of threshold settings in the IED.