Simulation and Comparative Analysis of NoC Routers and TileLink as Interconnects for OpenPiton

Abstract: In recent years, the world has moved towards multicore processing architecture to meet the ever growing need for high performance computing.The Industry using its industrial knowledge and resources have been building larger, more complex, manycore processors. Academic projects attempting to do the same face difficulties in replicating a similar scale of projects. In order to bridge this gap, OpenPiton was introduced as an opensource, general-purpose, multithreaded, manycore processor framework. It was designed to enable scalable architecture research prototypes from 1 core to 500 million cores.In order to take advantage of the capabilities of multicore processors, each core on the processor needs to be able to communicate effectively to work efficiently and ensure smooth operation. Not only is there a need for good intra-chip networks for communication between cores, but also a good network to communicate with off-chip interfaces. This network that can be used to communicate with on-chip and off-chip interfaces is called an Interconnect.In this thesis, the timing properties and the inner working principle of OpenPiton's Interconnect, i.e., NoC Routers, is compared to an opensource interconnect called TileLink. Although the initial challenge was to replace the interconnect in OpenPiton with TileLink, the topic of the thesis pivoted towards analysing and determining feasibility of replacing NoC routers with TileLink while discussing the merits and challenges that one might encounter in such an endavour.In this thesis, it was found that the code and the functioning for the Interconnect in OpenPiton was closely connected to the cache. A rewrite of how the cache and the interconnect are connected is necessary in order to safely replace it with any alternatives. This rewrite should also ensure that any modifications that are made to the code-base are compatible with the tools used by OpenPiton to generate processor prototypes.