Area and Power Efficiency of Multiplier-Free Finite Impulse Response Filters

Abstract: In digital radio systems, a large number of finite impulse response filters are typically used. Due to their nature of operation, such filters require many multiplication operations, leading to great costs in terms of both chip area and power consumption. For cost reduction reasons, there is a strong business case for implementing these filters without general multipliers so as to reduce the area and power consumption of the overall system.This thesis explores a method of implementing finite impulse response halfband filters without general multipliers, by using a special filter structure and replacing multipliers with sequences of binary shifts and additions. The savings in terms of area and power consumption are estimated and compared to a conventional filter (with a common structure) implementation containing general multipliers, as well as the same conventional filter implemented without general multipliers by means of manipulating its coefficients such that they can be implemented with shifts and additions.The results show that while using the special filter structure with shifts and additions consumes less area and power than a conventional filter with general multipliers, employing simpler methods to obtain coefficients implementable with shifts and additions in a conventional filter structure produces smaller filters consuming less power. Moreover, the results of this thesis show that using methods allowing for multiplier-free filter implementations with conventional filter structures seems favorable, hence further investigation of such methods is recommended. Future studies could also focus on methods applicable to filters with support for dynamic coefficients.