Evaluation of flexible SPA based LPDC decoder using hardware friendly approximation methods
Abstract: Due to computation-intensive nature of LDPC decoders, a lot of research is going towards eﬃcient implementation of their original algorithm (SPA). As "Min-Sum" approximation is basically an overestimation of SPA, this thesis investigates more accurate, yet area eﬃcient, approximations of SPA, to select an optimum one. In a general comparison between main approximation methods (e.g. LUT, PWL, CRI), PWL showed the most area-eﬃciency. Studying diﬀerent mathematical formats of SPA, Soft-XOR based format with forward-backward scheme was chosen for hard- ware implementation. Its core function (Soft-XOR) was implemented with CRI approximation, which achieved the highest eﬃciency, compare to other approxi- mations. Using this core function, a ﬂexible, pipe-lined, Soft-XOR based CNU (the computational unit of LDPC decoders) with forward-backward architecture was developed in 18nm CMOS. The implemented CNU’s area and speed can eas- ily be changed in instantiation. A SPA decoder based on the developed CNU was estimated to have an area of 1.6M as equivalent gate count and a throughput of 10Gb/s, with a frequency of 1.25GHz and for 10 iterations. The decoder uses IEEE 802.11n Wi-Fi standard with ﬂooding schedule. The BER/SNR loss, com- pare to ﬂoating-point SPA, is 0.3dB for 10 iterations and less than 0.1dB for 20 iterations.
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