Work function engineering for high temperature FD-SOI transistors

Abstract: Various applications require the MOSFETs that work at a high temperature which is ambient operating temperature higher than 125 ℃. However, the traditional bulk MOSFETs at high temperature suffers from high leakage currents and threshold voltage shift, thus the performance of the bulk MOSFETs is severely degraded. The excellent electrostatic control offered by silicon-on-insulator (SOI) MOSFETs enables electronics that can operate at high temperature. Previous work has fabricated fully depleted SOI (FDSOI) MOSFETs with the poly-silicon/TiN-gate stack, which showed that the gate stack provided an appropriate threshold voltage for P-FETs, but N-FETs threshold voltage was too low, causing the off-state leakage current to be too high at high temperature.  This project tries to modify the gate stack for N-FETs to reach a proper threshold voltage value for high-temperature applications. A gate stack with a different structure was fabricated on a p-type bulk Si wafer to demonstrated the flat-band voltage can be separated by selectively remove the TiN layer using the wet etching process. A n+-poly-Si/TiN and n+-poly-Si gate stack was fabricated and C-V measurement revealed a flat-band voltage of -0.6 V for n+-poly-Si/TiN and -0.75 V for n+-poly-Si gate stack.  These promising early results suggest that further investigations are warranted. Future work can include investigating replacing n+-poly with p+-poly, wet etching at higher temperature, and finally fabricate SOI MOSFETs using the proposed process flow.