Capacitive Crosstalk Effects on On-Chip Interconnect Latencies and Data-Rates

Abstract: This thesis work investigates the effects of crosstalk on on-chip interconnects. We use optimal repeater insertion as a reference and derive analytical expressions for signal latency, maximum data-rate and power consumption. Through calculations and simulations we show that despite large uncertainties in arrival time of a signal that is subject to crosstalk, we are able to make predictions about the maximum data-rate on a bus. We also show that data-rates can exceed the classical limit of the latency inverted by using wave pipelining. To increase the data-rate, we can increase the number of repeaters to a limit, at the cost of additional latency and power. Savings in power consumption can be achieved by using fewer repeaters, paying in latency and data-rate. Through fewer repeaters, the top metal layer shows better performance in all investigated aspects.