Automated modelling and optimization of a ratioed logic inverter utilizing nanowire-based transistors

University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

Abstract: The continuing trend of electronic miniaturization is approaching a critical limit for conventional silicon based technology. Transistors based on nanowires are an interesting concept that might extend this trend deeper into the nano-scale domain. In this work, the usage of nanowire-based transistors is studied in the context of digital circuit design. The authors propose a complete workflow from measurement, through transistor modelling and circuit simulation to an optimized inverter design. This workflow is realized in the form a software suite, developed for this purpose. By implementing intelligent algorithms and extraction methods, this allows the workflow to be highly automated, reducing the time needed for a complete analysis from weeks to a matter of minutes. A modified MOSFET model is introduced based on the proper deep-submicron MOSFET model. By adding a series resistance and introducing a dependence on the nanowire quantity in addition to neglecting the channel length modulation, the Jansson-Berg model is defined. The model is implemented into the software and an acceptable correspondence to measurement data is achieved. To simulate the parasitic capacitances in the transistor design, a model consisting of 21 separate capacitances is derived. The Jansson-Berg model is analysed in the application of simulating an inverter. Due to the unavailability of p-type transistors, a ratioed logic design is proposed, utilizing only n-type transistors. As an exact analytical solution of the circuit performance is nearly impossible, it is concluded that series solutions are necessary. Although simplifications are made, the analytical solutions achieve a good correspondence to a purely numerical analysis. Finally, the transistor design is optimized based on the energy-delay product. This is done intelligently, by testing about 300 million transistor designs, bound by specified design rules. Based on this large data set, it is concluded that further downscaling is advisable.

  AT THIS PAGE YOU CAN DOWNLOAD THE WHOLE ESSAY. (follow the link to the next page)