Test Vector Extraction Methodology For Power Integrity Analysis
Abstract: In order to decrease performance pessimism due to supply voltage uncertainties inintegrated circuits, detailed power integrity analysis is necessary. Knowing the worstcasevoltage drop that the circuit will encounter is a step towards this goal. Thevoltage drop is input-dependent, which means the outcome depends on how the chipis used.In this thesis, methods to extract the worst-case clock cycle out of a microprocessorrun-trace are developed. The methods considered are based on time-based powersimulations, considering full-chip total power in several time-resolutions, frequencybased approaches using FFT and wavelets, and the spatial locality of switching activity.SPICE voltage drop simulations are performed while considering R and Lcomponents of the power grid, as well as decoupling capacitance and the gate switchingextracted from the run-trace.Results show that the voltage drops found when focusing on spatial locality exceedthe previous worst-case for the chip design by a factor of 2. This method considersthe worst-case power grid node, finding the time-instance where maximum power dissipationof its adjacent nodes coincides with the maximum power dissipation of thechip’s CPU core.Attempts at alleviating these sparse and localized large voltage drops are performedthrough the use of skew-spreading. This method is shown to decrease the largestvoltage drop found by over 20%.
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