Ultra-Low Power Input Driver for High-ResolutionDiscrete-Time Σ∆ Modulator
This thesis presents the design of an input driver for ultra-low power sigmadelta modulator. High resolution Σ∆ ADCs are becoming more and more usefulin ultra-low power medical applications. Therefore, reducing supply voltage andpower starts a new chanllenges both at architecture as well as circuit performancelevel. Three input drivers are presented in this thesis making use of operationalampliﬁers with the class AB buﬀers as output stage.In the thesis, the building blocks of the input buﬀer are described in detail.Two diﬀerent designs are included in the thesis in order to achieve the speciﬁcationunder diﬀerent conditions of the input signal. The speciﬁcations are 90 dB Signalto-Noiseand Distortion Ratio (SNDR) and 4 µW of the power consumption. Atwo stage achitectures with diﬀerent building blocks is investigated. The buildingblocks are a single stage fully diﬀerential ampliﬁer as the ﬁrst stage and a classAB behavior unity gain buﬀer as the second stage. Design comparison is basedon the simulation results. The reasons for the diﬀerent designs are mainly causedby design constraints, the input signal voltage level and the stability. Designconstraints are because of the trade-oﬀs among structure of the building block,transistor threshold voltage and low power supply voltage. At the end of thisthesis project, we achieved 90dB SNDR in the ﬁrst design by using Folded-VoltageFollower (FVF) structure in transistor level and an improved performance designin the second design.
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