Ultra-Low Power Input Driver for High-ResolutionDiscrete-Time Σ∆ Modulator

Abstract: This thesis presents the design of an input driver for ultra-low power sigmadelta modulator. High resolution Σ∆ ADCs are becoming more and more usefulin ultra-low power medical applications. Therefore, reducing supply voltage andpower starts a new chanllenges both at architecture as well as circuit performancelevel. Three input drivers are presented in this thesis making use of operationalamplifiers with the class AB buffers as output stage.In the thesis, the building blocks of the input buffer are described in detail.Two different designs are included in the thesis in order to achieve the specificationunder different conditions of the input signal. The specifications are 90 dB Signalto-Noiseand Distortion Ratio (SNDR) and 4 µW of the power consumption. Atwo stage achitectures with different building blocks is investigated. The buildingblocks are a single stage fully differential amplifier as the first stage and a classAB behavior unity gain buffer as the second stage. Design comparison is basedon the simulation results. The reasons for the different designs are mainly causedby design constraints, the input signal voltage level and the stability. Designconstraints are because of the trade-offs among structure of the building block,transistor threshold voltage and low power supply voltage. At the end of thisthesis project, we achieved 90dB SNDR in the first design by using Folded-VoltageFollower (FVF) structure in transistor level and an improved performance designin the second design.