Design of an Operational Amplifier for High Performance Pipelined ADCs in 65nm CMOS
In this work, a fully differential Operational Amplifier (OpAmp) with high Gain-Bandwidth (GBW), high linearity and Signal-to-Noise ratio (SNR) has been designed in 65nm CMOS technology with 1.1v supply voltage. The performance of the OpAmp is evaluated using Cadence and Matlab simulations and it satisfies the stringent requirements on the amplifier to be used in a 12-bit pipelined ADC. The open-loop DC-gain of the OpAmp is 72.35 dB with unity-frequency of 4.077 GHz. Phase-Margin (PM) of the amplifier is equal to 76 degree. Applying maximum input swing to the amplifier, it settles within 0.5 LSB error of its final value in less than 4.5 ns. SNR value of the OpAmp is calculated for different input frequencies and amplitudes and it stays above 100 dB for frequencies up to 320MHz.
The main focus in this work is the OpAmp design to meet the requirements needed for the 12-bit pipelined ADC. The OpAmp provides enough closed-loop bandwidth to accommodate a high speed ADC (around 300MSPS) with very low gain error to match the accuracy of the 12-bit resolution ADC. The amplifier is placed in a pipelined ADC with 2.5 bit-per-stage (bps) architecture to check for its functionality. Considering only the errors introduced to the ADC by the OpAmp, the Effective Number of Bits (ENOB) stays higher than 11 bit and the SNR is verified to be higher than 72 dB for sampling frequencies up to 320 MHz.
AT THIS PAGE YOU CAN DOWNLOAD THE WHOLE ESSAY. (follow the link to the next page)