Temperature Dependent Electrical Characterisation of Vertical InAs-InGaAs Nanowire MOSFETs

Abstract: This thesis presents the temperature dependence of InGaAs Nanowire (NW) metal-oxide-semiconductor field-effect transistors (MOSFETs) grown at two different temperatures. The two different growths represent one sample having nanowires which have a mixed crystal structure (showing stacking faults) and one sample with nanowires of pure crystal structure (without stacking faults). The sample with a pure crystal structure was grown at a higher temperature. Both Direct current (DC) and Low-frequency (LF) noise measurements were made on the best devices on the two samples. The DC measurements were made at temperatures ranging from a room temperature of 293 K to a cryogenic temperature of 14 K. The DC characteristics at room temperature show maximum transconductance of and a SS of for the sample with stacking faults and and for the sample without. At 14 K the SS went down to and correspondingly. The LF noise characterization was made at room temperature as well as at a cryogenic temperature of 14 K. The dominant noise source for both samples at room temperature is number fluctuations. The minimum trap density at 10 Hz for the sample with stacking faults was and for the sample without. Measurements made at the cryogenic temperature showed implications of mobility fluctuations being the dominant noise source instead of number fluctuations. The Hooge parameter for the sample with stacking faults was independent of current and was calculated to. For the sample without stacking faults the Hooge parameter varied with the current and was calculated between and. This study does not give any implication that a mix in the crystal structure in InGaAs NW gives any down-grade in performance in terms of subthreshold swing and LF noise.