Design and implementation of testable fault-tolerant RISC-V system
Abstract: This thesis aims to investigate and implement a fault-tolerant energy-efficient RISC-V based system on chip (SoC). Key features of the SoC is the testabil- ity and reliability of the low power on-chip embedded memories. A built-in self- test (BIST) for the on-chip memories has been designed and implemented to run on-demand diagnostic tests to detect manufacturing errors in the memories. It incorporates three different algorithms to test for common manufacturing memory faults. Runtime soft errors are detected and corrected using an error correction code unit (ECC), which can correct up to two errors. The ECC is integrated with the RISC-V core and memories to increase the fault-tolerance of the SoC at low voltages. The ECC components importance increases as the probability of soft errors increase with lowering of the supply voltage. Power savings up to 46% for the entire system was simulated when the supply voltage was decreased from 1.2V down to 0.8V. The addition of the ECC components resulted in a 3.5% core area increase. The integrated memory built-in self-test contributed to another 24.4% area increase of the core.
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