Low power memory controller subsystem IP exploration using RTL power flow : An End-to-end power analysis and reduction Methodology

University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

Abstract: With FinFET based Application Specific Integrated Circuit (ASIC) designs delivering on the promises of scalability, performance, and power, the road ahead is bumpy with technical challenges in building efficient ASICs. Designers can no longer rely on the ‘auto-scaling’ power reduction that follows technology node scaling, in these times when 7nm presents itself as a ‘long-lived’ node. This leads to the need for early power analysis and reduction flows that are incorporated into the ASIC Intellectual Property (IP) design flow. This leads to a focus on power-efficient design in addition to being functionally efficient. Power inefficiency related hotspots are the leading causes of chip re-spins, and a guideline methodology to design blocks in a power-efficient manner leads to a power-efficient design of the Integrated Circuits (ICs). This alleviates the intensity of cooling requirements and the cost. The Common Memory controller is one of the leading consumers of power in the ASIC designs at Ericsson. This Thesis focusses on developing a power analysis and reduction flow for the common memory controller by connecting the verification environment of the block to low-level power analysis tools, using motivated test cases to collect power metrics, thereby leading to two main goals of the Thesis, characterization and optimization of the block for power. This work also includes an energy efficiency perspective through the Differential Energy Analysis technique, initiated by Qualcomm and Ansys, to improve the flow by improving the test cases that help uncover power inefficiencies/bugs and therefore optimize the block. The flow developed in the Thesis fulfills the goals of characterizing and optimizing the block. The characterization data is presented to provide an idea of the type of data that can be collected and useful for SoC architects and designers in planning for future designs. The characterization/profiling data collected from the blocks collectively contribute to the Electronic System-level power analysis that helps correlate the ASIC power estimate to silicon. The work also validates the flow by working on a specific sub-block, identifying possible power bugs, modifying the design and validating improved performance and thereby, validating the flow.

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