Design of a 30 GHz PLL for use in Phased Arrays
Abstract: This project includes the research and implementation of a high frequency phase-locked loop (30 GHz or more) for beamforming use in a phased antenna array. The phase-locked loop includes a quadrature voltagecontrolled oscillator with a 10% tuning range and 417 degrees of phase control with a 10 degree resolution, a current mode latch in the divide-bytwo configuration operates over the quadrature voltage-controlled oscillator’s tuning range while consuming less than 583 uA of current, Dtype flip flops in a divide-by-8 configuration, a phase-frequency detector, a charge-pump, and a loop filter. The quadrature voltage-controlled oscillator has a phase noise of -102.2 dBc/Hz at 1 MHz, less than 3.53 mA current consumption, and up to 185.6 dBc/Hz figure of merit. Additionally, an injection-locked frequency divider was explored as an optional first-stage divider. The phase-locked loop was implemented using the ST Microelectronics 65 nanometer design kit and simulated using Cadence Virtuoso. The circuit consumes 4.93 mA of current from a 1.2 V supply. Lastly, the bottlenecks that may be encountered while increasing the operating frequency of the phase-locked loop are discussed.
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