Partial Reconfiguration of a CPRI Implementation on an FPGA

Abstract: Utilizing Partial Reconfiguration (PR) in Field Programmable Gate Arrays (FPGAs) is a digital hardware design concept that has gained in popularity and ease of implementation over the past decades. In short, it means that a limited region of the FPGA is reconfigured during run-time depending on which logic is needed at a given time. This way, the logic utilization of the FPGA can be reduced while still maintaining the same functionality in designs where certain logic blocks are not run in parallel. For example, it has previously proven to be useful in designs containing several types of hardware accelerators which are used by a Central Processing Unit (CPU). Common Public Radio Interface (CPRI) is a communication interface between components of a Radio Base Station (RBS); Radio Equipment (RE) and Radio Equipment Control (REC). The specification of the interface outlines a functional split between two different layers. In this master’s thesis, the potential benefits and challenges of applying the concept of Partial Reconfiguration to a CPRI layer 2 FPGA design are investigated. Using an Intel Arria 10 development board, a platform has been designed for evaluation of relevant parameters with focus on resource utilization, bitstream file size and reconfiguration time. The results do not show clear benefits of utilizing PR in this particular block, mainly due to the fact that not a large reduction of logic utilization is achieved compared to a reference implementation of the block where PR is not utilized. However, important insights for future work on PR implementation of similar circuits have been obtained.