Modelling a memory

Abstract: The purpose of this master thesis is to describe the work behind the building of a scalable model of a memory designed at Zarlink Semiconductor AB. This model is to be part of a memory generator and used to extract timing parameters for all available memory sizes instead of simulating the layout, as layout simulation takes too much time. The report starts with the basic theory of passive circuit elements that has to be considered in a model and what effect these elements have on functionality and robustness of the design. There’s also a short chapter on how to layout for optimisation towards high speed, minimal area or low power consumption. After that, the work behind three different models of a memory is described. The models are a skeletal model, a mixed-mode model and a digital model. The skeletal model was the only one that could be finished and this model is then evaluated and compared to a simulation made on the original layout of the memory. Included in the description of the mixed-mode and digital models are a description of how you characterise cells and how you include power information in digital simulation. At the end there’s a short chapter on the future of modelmaking.