Design and Implementation of a Low-Power Random Access Memory Generator

Abstract: In this thesis, a Static Random Access Memory generator has been designed and implemented. The tool can generate memories of different sizes. The number of words that can be stored can be chosen among powers of 2 and the number of bits per word can be up to 48. The focus of the thesis was to find an adequate structure for the generated memories depending on the size, and develop a memory generator that implements the structures, which has been thoroughly done. The single circuits used in the generated memories can be substituted with better circuits as well as adapted to other processes. All circuits apart from a block decoder circuit have been developed. The memory generator was not supposed to automatically produce a complete layout, and some manual interventions on the memories generated by the tool are necessary. The tool requires to be developed further to minimise this manual intervention on the generated memories. The complete memories generated have not been tested because of their complexity, but tests on circuits as well as many parts of the memories have been carried out. During the thesis work, a large amount of tasks had to be carried out and a lot of issues had to be dealt with, which has been a problem. The tool used for the implementation has powerful features for both analog and digital electronic design, but has stability problems with large designs, which has been a big obstacle in this work.