FPGA Implementation of an Interpolator for PWM applications

Abstract: In this thesis, a multirate realization of an interpolation operation is explored. As one of the requirements for proper functionality of the digital pulse-width modulator, a 16-bit digital input signal is to be upsampled 32 times. To obtain the required oversampling ratio, five separate interpolator stages were designed and implemented. Each interpolator stage performed uppsampling by a factor of two followed by an image-rejection lowpass FIR filter. Since, each individual interpolator stage upsamples the input signal by a factor of two, interpolation filters were realized as a half-band FIR filters. This kind of linear-phase FIR filters have a nice property of having every other filter coefficient equal to zero except for the middle one which equals 0.5. By utilizing the half-band FIR filters for the actual realization of the interpolation filters, the overall computational complexity was substantially reduced. In addition, several multirate techniques have been utilized for deriving more efficient interpolator structures. Hence, the impulse response of individual interpolator filters was rewritten into its corresponding polyphase form. This further simplifies the interpolator realization. To eliminate multiplication by 0.5 in one of two polyphase subfilters, the filter gain was deliberately increased by a factor of two. Thus, one polyphase path only contained delay elements. In addition, for the realization of filter multipliers, a multiple constant multiplication, (MCM), algorithm was utilized. The idea behind the MCM algorithm, was to perform multiplication operations as a number of addition operations and appropriate input signal shifts. As a result, less hardware was needed for the actual interpolation chain implementation. For the correct functionality of the interpolator chain, scaling coefficients were introduced into the each interpolation stage. This is done in order to reduce the possibility of overflow. For the scaling process, a safe scaling method was used. The actual quantization noise generated by the interpolator chain was also estimated and appropriate system adjustments were performed.