Evaluating the performance of FPGA-based Secure Hash Algorithms for use in SPHINCS+

Abstract: In the digital landscape of today, large amounts of transactions, messaging and different kinds of authorizations are carried out online. To ensure the the integrity and security of these systems, digital signature systems are used to verify the identity of different individuals and entities. As quantum computing threatens to compromise contemporary signature schemes, a new generation of quantum secure signature schemes have been developed. One such scheme is SPHINCS+, which uses hash algorithms to generate and verify its signatures. This study aims to evaluate the utilization of a Field Programmable Gate Array (FPGA) to increase the processing speed of these hash algorithms, thus potentially increasing the speed of the entire signature scheme. The research methodology consisted of implementing the hash algorithms SHA-2 and SHA-3, used in SPHINCS+, on an FPGA. Variations of these implementations were created, utilizing parallelism as well as an efficient hardware pipeline in order to enhance the efficiency of the algorithms. All implementations were then benchmarked against each other and corresponding CPU implementations. The results show that the FPGA solutions increased hash computation times compared to the CPU implementations. While SHA-3 generally showed higher performance than SHA-2, the overall performance drop of both algorithms was significant, suggesting that the implementations require further optimizations in order to be used to accelerate SPHINCS+.