Essays about: "SRAM design"
Showing result 16 - 20 of 20 essays containing the words SRAM design.
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16. Multilevel Gain Cell Arrays for Fault-Tolerant VLSI Systems
University essay from ElektroniksystemAbstract : Embedded memories dominate area, power and cost of modern very large scale integrated circuits system on chips ( VLSI SoCs). Furthermore, due to process variations, it becomes challenging to design reliable energy efficient systems. Therefore, fault-tolerant designs will be area efficient, cost effective and have low power consumption. READ MORE
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17. Design and Evaluation of A Low-Voltage, Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology
University essay from Institutionen för systemteknikAbstract : This thesis presents a novel six-transistor SRAM intended for advanced microprocessor cache application. The objectives are to reduce power consumption through scaling the supply voltage and to design a SRAM that is fully process-variation-tolerant, utilizing separate read and write access ports as well as exploiting asymmetry. READ MORE
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18. Implementation of a Zero Aware SRAM Cell for a Low Power RAM Generator
University essay from Institutionen för systemteknikAbstract : In this work, an existing generator for layout of Static Random Access Memory (SRAM) is improved. The tool is completed with a block decoder, which was missing when the thesis started. A feature of generating schematic files is also added. READ MORE
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19. Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors
University essay from Institutionen för systemteknikAbstract : This thesis presents a five-transistor SRAM intended for the advanced microprocessor cache market. The goal is to reduce the area of the cache memory array while maintaining competitive performance. Various existing technologies are briefly discussed with their strengths and weaknesses. READ MORE
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20. Design and Implementation of a Low-Power Random Access Memory Generator
University essay from Institutionen för systemteknikAbstract : In this thesis, a Static Random Access Memory generator has been designed and implemented. The tool can generate memories of different sizes. The number of words that can be stored can be chosen among powers of 2 and the number of bits per word can be up to 48. READ MORE
