Essays about: "formell verifiering"
Showing result 1 - 5 of 18 essays containing the words formell verifiering.
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1. Improving the Synthesis of Annotations for Partially Automated Deductive Verification
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : This work investigates possible improvements to an existing annotation inference tool. The tool is part of a toolchain that aims to automate the process of software verification using formal methods. READ MORE
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2. Practical Analysis of the Giskard Consensus Protoco
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Consensus protocols are the core of modern blockchain systems, such as the Bitcoin, Ethereum, and Algorand networks. Thanks to these protocols, participants in a blockchain network can reach consensus on which blocks to add to a blockchain, to have a consistent chain of blocks in the whole network. READ MORE
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3. Automated Inference of ACSL Contracts for Programs with Heaps
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Contract inference consists in automatically computing contracts that formally describe the behaviour of program functions. Contracts are used in deductive verification, which is a method for verifying whether a system behaves according to a provided specification. The Saida plugin in Frama-C is a contract inference tool for C code. READ MORE
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4. Applications of Formal Explanations in ML
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : The most performant Machine Learning (ML) classifiers have been labeled black-boxes due to the complexity of their decision process. eXplainable Artificial Intelligence (XAI) methods aim to alleviate this issue by crafting an interpretable explanation for a models prediction. READ MORE
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5. Validation of efficiency of formal verification methodology for verification closure
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) verification is quite a time consuming phase in design flow cycle and it can be done using methodologies such as Universal Verification Methodology (UVM) and formal verification.The UVM methodology is simulation based verification where in the verifier will have to trigger the Design Under Test (DUT) manually by writing sequences which target different features of the DUT and the verification environment can also have verification directives such as assertions to spot design bugs. READ MORE