Essays about: "master thesis in vhdl"

Showing result 1 - 5 of 19 essays containing the words master thesis in vhdl.

1. 1. Novel Method of ASIC interface IP development using HLS

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Anestis Athanasiadis; Chandranshu Mishra; [2023]
   Keywords : High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

   Abstract : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. READ MORE

3. 2. Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Kevin Skaria Chacko; [2019]
   Keywords : Technology and Engineering;

   Abstract : This Master’s thesis aims to conduct a case study on using Universal Verification Methodology (UVM) in SystemC for Register-Transfer Level (RTL) verification. Verification of ASICs is very important nowadays especially in terms of production costs, time to market and the sustainability of products. READ MORE

4. 3. Design and implementation of a high-speed PCI-Express bridge

   University essay from Linköpings universitet/Fysik, elektroteknik och matematik; Linköpings universitet/Tekniska fakulteten

   Author : Mandus Börjesson; Håkan Gerner; [2019]
   Keywords : FPGA; PCI Express; M.2; High-speed PCB Design; LVDS; CMOS; Bridge; Protocol; Artix-7; VHDL; SMBus;

   Abstract : This master thesis will cover the prestudy, hardware selection, design and implementation of a PCI Express bridge in the M.2 form factor. The thesis subject was proposed by WISI Norden who wished to extend the functionality of their hardware using an M.2 module. READ MORE

5. 4. Robust and flexible hardware implementation of ITU-G4

   University essay from Mittuniversitetet/Avdelningen för elektronikkonstruktion

   Author : Aart Mulder; [2014]
   Keywords : VHDL; Image compression; Fax4; ITU-G4;

   Abstract : This project was carried out as thesis work during the last semester of my Master studies Electronics Design at the Mid Sweden University. Firstly, it considers a robust and exible implementation of ITU-G4 in hardware based on earlier work, and secondly, it covers review of related work and investigation in the weaknesses of two published designs. READ MORE

6. 5. CAN signal quality analysis and development of the signal processing on a FPGA

   University essay from Linköpings universitet/Fysik och elektroteknik; Linköpings universitet/Tekniska högskolan

   Author : Jakob Uhlin; [2014]
   Keywords : FPGA; CAN-bus analyzer; CAN; signal theory;

   Abstract : This master thesis report is a part of the thesis project conducted by Jakob Uhlin at Syntronic R R and D, Stockholm Sweden. The objective of this thesis is to develop a way to process the signal being sent on a CAN-bus and subsequently analyse its quality and its source in the network. READ MORE