PLL for 5G mmWave

Abstract: This paper presents research and implementation of a high frequency Integer-N phase-locked loop for digital beamforming in mobile devices. Multiple topologies investigated whereof two were implemented. The transient phase noise of the PLL is -104dB/-95dB @1MHz. The output frequency range is from 8G-10G. Reference signal is 163.84MHz, reference-spurs is -80dBc/-98dBc lower than main frequency. RMS jitter is about 38fs/68fs. Locking time is less than 3.5us. The implementation consists of an LC-tank VCO with extra tail filtering. Divider chain consisting of a dual module prescaler/CML prescaler followed by a programmable divider. Charge pump with compensation method and a cascoded gain-boosting charge pump is used to decrease current mismatch. Tri-state phase detector and lastly a third-order passive loop filter. Supply voltage at 0.8V is used in the design. Total power consumption is less than 10mW. The PLL system was implemented in the CMOS FD-SOI 22nm process and simulations executed in the Virtuoso Cadence environment. Limitations and possible improvements are listed in the end.