A Dataplane Programmable Traffic Marker using Packet Value Concept

Abstract: Real-time sensitive network applications are emerging and require ultra-low latency to reach the desired QoS. A main issue that contributes to latency is excessive buffering at intermediate switches and routers. Existing queuing strategies that aim to reduce buffering induced latency typically apply a single queue AQM that does not support service differentiation and treats all packets equally. The recently proposed per packet value framework utilizes a packet value marker and a packet value aware AQM to solve this issue by supporting service differentiation in a single queue and introducing more advanced policies for resource sharing. However, the per packet value framework is implemented and tested in a software environment with no possibility to study the performance on hardware equipment.  This thesis utilizes P4 to design and implement a packet value marker on dataplane programmable devices. The marker should be capable of supporting multiple resource sharing policies, following resource sharing policies accurately, and not being the bottleneck in the network. A target-independent packet value marker is designed and modified with target-dependent P4 constructs to fit the implementation requirements of a Tofino switch and a Netronome smart NIC. An accurate Tofino implementation using this approach is difficult to achieve because of a complicated random number generation process and resource limitation. Evaluation using a testbed with a Netronome marker shows that the marker achieves desired functionality with accurate packet value distribution for throughputs larger than 5000 Kbps. However, the challenge of concurrent packet processing combined with a smart NIC that does not have powerful packet processing cores results in the marker having lower throughput and higher latency than expected. The evaluation also shows that resource limitation in terms of available memory and the number of supported policies affects the maximum number of supported users. We also ported a version to a switching ASIC with limited functionality due to the restrictions of the hardware platform. Our evaluation also provides insights into how such a marking scheme performs on different hardware targets and the limitation imposed by such target specific architecture.