Short Message Network-On-Chip Interconnect for ASIC

Abstract: The rise of large scale integration has resulted in large number of processing elements/cores on a single ASIC. Thus an efficient interconnect scheme between the different processing elements and interfaces is required. Bus based interconnect poses problems such as non-scalability. This thesis explores the Network-on-Chip (NOC) as a global interconnect scheme on a state of the art ASIC. Different On-chip interconnect techniques proposed by the academia/industry are summarized and Design space exploration of NOC schemes is performed. A Network-on-Chip interconnect, primarily utilized for short messaging service between the processing elements/nodes in the ASIC, is designed for Ericsson ASICs. Practical ASIC design issues such as non-uniform network topology (irregular mesh) and performance immunity of interconnect due to variations in the floorplan are addressed in the NOC design. The proposed Network-on-chip interconnect for Ericsson ASICs is evaluated in terms of varying traffic models, routing algorithms, NOC router FIFO depths and floor plans. The SystemC cycle accurate performance results of NOC are compared with the currently implemented Bus based solution for the Ericsson ASIC.