Digital Image Processing Algorithms Research Based on FPGA

Abstract: As we can find through the development of TV systems in America, the digital TV related digital broadcasting is just the road we would walk into. Nowadays digital television is prevailing in China, and the government is promoting the popularity of digital television. However, because of the economic development, analog television will still take its place in the TV market during a long period. But the broadcasting system has not been reformed, as a result, we should not only take use of the traditional analog system we already have, but also improve the quality of the pictures of analog system. With the high-speed development of high-end television, the research and application of digital television technique, the flaws caused by interlaced scan in traditional analog television, such as color-crawling, flicker and fast-moved object's boundary blur and zigzag, are more and more obvious. Therefore the conversion of interlaced scan to progressing scan, which is de-interlacing, is an important part of current television production. At present there are many kinds of TV sets appearing in the market. They are based on digital processing technology and use various digital methods to process the interlaced, low-field rate video data, including the de-interlacing and field rate conversion. The digital process chip of television is the heart of the new-fashioned TV set, and is the reason of visual quality improvement. As a requirement of real time television signal processing, most of these chips has developed novel hardware architecture or data processing algorithm. So far, the most quality effective algorithm is based on motion compensation, in which motion detection and motion estimation will be inevitably involved, in despite of the high computation cost. in video processing chips, the performance and complexity of motion estimation algorithm have a direct impact on speed area and power consumption of chips. Also, motion estimation determined the efficiency of the coding algorithms in video compression. This thesis proposes a Down-sampled Diamond NTSS algorithm (DSD-NTSS) based on New Three Step Search (NTSS) algorithm, taking both performance and complexity of motion estimation algorithms into consideration. The proposed DSD-NTSS algorithm makes use of the similarity of neighboring pixels in the same image and down-samples pixels in the reference blocks with the decussate pattern to reduce the computation cost. Experiment results show that DSD-NTSS is a better tradeoff in the terms of performance and complexity. The proposed DSD-NTSS reduces the computation cost by half compared with NTSS when having the equivalent image quality. Further compared with Four Step Search(FSS) Diamond Search(DS)、Three Step Search(TSS) and some other fast searching algorithms, the proposed DSD-NTSS generally surpasses in performance and complexity. This thesis focuses on a novel computation-release motion estimation algorithm in video post-processing system and researches the FPGA design of the system.