An Integrated High Efficiency DC-DC Converter in 65 nm CMOS
This thesis work describes the implementation perspective of an integrated high efficiency DC-DC converter implemented in 65 nm CMOS. The implemented system employs the Buck converter topology to down-convert the input battery voltages. This converter offers its use as a power management unit in portable battery operated devices.
This thesis work includes the description of a basic Buck converter along with the various key equations involved which describe the Buck operation as well as are used to deduce the requirements for the various internal building blocks of the system. A detailed description of the operation as well as the design of each of the building blocks is included.
The implemented system can convert the input battery voltage in the range of 2.3 V to 3.6 V into an output supply voltage of 1.6 V. The system uses dual-mode feedback control to maintain the output voltage at 1.6 V. For the low load currents the PFM feedback control is used and for the higher load currents the PWM feedback control is used. This converter can supply load currents from 0 to 300 mA with efficiency above 85%. The static line regulation of the system is < 0.1% and the load regulation of the system is < 0.3%. A digital soft-start circuit is implemented in this system. The system also includes the capability to trim the output voltage in ~14 mV steps depending on the 4-bit input digital code.
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