Testing Platform for Memory IPs using PULPissimo

Abstract: Memory IPs are important components in SoC designs. Hence, making sure that the memory IPs are functioning as expected is crucial for any organization. In order to do so, memory IPs must be tested. In addition, the testing capabilities can be enhanced by integrating a processor to the memory test chip. In this project, an open-source PULPissimo platform based on RISC-V ISA(Instruction set architecture) is used as this gives freedom to the system designer and the organization to configure the processor core as per the requirements. Further in this project, various checksum algorithms such as MD5, SHA-1 and SHA-256 are implemented in RTL which can be used to test the organization’s ROM IPs. Subsequently, each of the algorithms are integrated to the PULPissimo to provide a platform for testing the ROM IPs. Finally, various comparisons are made using synthesized results. The three implemented algorithms are compared with respect to the number of gates used and latency to identify the suitable algorithm for the organization. Similarly, the cores in the PULPissimo are also compared to identify the preferable core to be used by the organization.