Design of a Gigabit Router Packet Buffer using DDR SDRAM Memory

Abstract: The computer engineering department at Linköping University has a research project which investigates the use of an on-chip network in a router. There has been an implementation of it in a FPGA and for this router there is a need for buffer memory. This thesis extends the router design with a DDR memory controller which uses the features provided by the Virtex-II FPGA family. The thesis shows that by carefully scheduling the DDR SDRAM memory high volume transfers are possible and the memory can be used quite effciently despite its rather complex interface. The DDR memory controller developed is part of a packet buffer module which is integrated and tested with a previous, slightly modifed, FPGA based router design. The performance of this router is investigated using real network interfaces and due to the poor network performance of desktop computers special hardware is developed for this purpose.