Design of a 12-bit 200-MSps SAR Analog-to-Digital converter

Abstract: The Successive Approximation (SAR) Analog-to-Digital converter is one of the most energy-efficient A/D converter. In this thesis, the development of a SAR ADC in a 28-nm CMOS technology based on charge redistribution is presented.The implemented SAR ADC uses a switching procedure based on a modified version of the mono- tonic switching algorithm to reduce the switching energy and area of the DAC. The DAC is a binary- weighted array of unit capacitors. A unit custom capacitor has been designed with a value of 0.8 fF to reduce the DAC energy consumption. Two comparators have been implemented, a dynamic comparator and a static comparator. The dynamic implementation allows to obtain better performance. Therefore, the dynamic comparator is chosen for the SAR ADC. The sampling switches are bootstrapped to reduce the non-linearity introduced when the input signal is sampled. The SAR operations are controlled by an asynchronous logic implemented as a behavioural model in Verilog-A.The effect of the designed circuits on the linearity of the converter is assessed with the integral non- linearity (INL) and differential non-linearity (DNL). Moreover, the performance of the ADC are assessed in terms of signal-to-noise-and-distortion ratio (SNDR). The co-simulation of Verilog-A behavioural models with circuit schematics allowed to evaluate the effect of each block on the overall performance of the ADC. The co-simulations show that the ADC is able to achieve an ENOB of 10.9 at a sampling rate of 200 MSps with a power consumption of 2.83 mW. The resulting FoM is 7.4 fJ/conv-step.