Essays about: "Hardware Verification"
Showing result 26 - 30 of 102 essays containing the words Hardware Verification.
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26. Automatic generation of network configuration in simulated time sensitive networking (TSN) applications
University essay from Mälardalens högskola/Inbyggda systemAbstract : The amount of data required to be processed in real-time embedded system is steadily increasing. This has caused industries to search for alternatives for reliable time-sensitive network communication. IEEE set of standards for Time-Sensitive Networking (TSN) is an attractive option for achieving this. READ MORE
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27. Simulation of Attitude and Orbit Control for APEX CubeSat
University essay from Luleå tekniska universitet/RymdteknikAbstract : CubeSats are becoming a game changer in the space industry. Appearing first for univer-sity mission, its popularity is increasing for commercial use and for deep space missionssuch as the on HERA mission that will orbit in 2026 around an asteroid as part of aplanetary defence mission. READ MORE
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28. High-Level Synthesis for Efficient Design and Verification
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : Designing hardware using High Level Synthesis automates parts of the digital hardware design process. By automating the process control is passed from the designer to the tool, thus it is highly important that the tool generates high performance hardware in terms of area and speed. READ MORE
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29. BB-EMU A Product Virtualizing System Verification of Embedded Hardware
University essay from Göteborgs universitet/Institutionen för data- och informationsteknikAbstract : The purpose of this study was to examine if there is a time difference when testing software on a physical embedded board and a virtualized version of the same board. This study conducted research on the topic at hand, organized experiments with the embedded boards and evaluated the results. READ MORE
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30. Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : This Master’s thesis aims to conduct a case study on using Universal Verification Methodology (UVM) in SystemC for Register-Transfer Level (RTL) verification. Verification of ASICs is very important nowadays especially in terms of production costs, time to market and the sustainability of products. READ MORE