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Showing result 1 - 5 of 25 essays matching the above criteria.

  1. 1. Deep Learning Model Deployment for Spaceborne Reconfigurable Hardware : A flexible acceleration approach

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Javier Ferre Martin; [2023]
    Keywords : Space Situational Awareness; Deep Learning; Convolutional Neural Networks; FieldProgrammable Gate Arrays; System-On-Chip; Computer Vision; Dynamic Partial Reconfiguration; High-Level Synthesis; Rymdsituationstänksamhet; Djupinlärning; Konvolutionsnätverk; Omkonfigurerbara Field-Programmable Gate Arrays FPGAs ; System-On-Chip SoC ; Datorseende; Dynamisk partiell omkonfigurering; Högnivåsyntes.;

    Abstract : Space debris and space situational awareness (SSA) have become growing concerns for national security and the sustainability of space operations, where timely detection and tracking of space objects is critical in preventing collision events. Traditional computer-vision algorithms have been used extensively to solve detection and tracking problems in flight, but recently deep learning approaches have seen widespread adoption in non-space related applications for their high accuracy. READ MORE

  3. 2. Optimizing the instruction scheduler of high-level synthesis tool

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Zihao Xu; [2023]
    Keywords : Instruction scheduling; Scheduling algorithm; CGRA; High-level Sythnesis; SiLago; Algorithm-level Synthesis; Constraint programming; Instruktion schemaläggning; schemaläggning algoritm; CGRA; High-level Sythnesis; SiLago; Algoritm-nivå Synthesis; Constraint programmering;

    Abstract : With the increasing complexity of the chip architecture design for meeting different application requirements, the corresponding instruction scheduler of high-level synthesis tool needs to solve complex scheduling problems. Dynamically Reconfigurable Resource Array (DRRA) is a novel architecture based on Coarse-Grained Reconfigurable Architecture (CGRA) on SiLago platform, the instruction scheduler of Vesyla-II, the dedicated High-Level Synthesis (HLS) tool targets for DRRA needs to schedule the specific instruction sets designed for Distributed Two-level Control System (D2LC). READ MORE

  4. 3. Novel Method of ASIC interface IP development using HLS

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Anestis Athanasiadis; Chandranshu Mishra; [2023]
    Keywords : High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

    Abstract : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. READ MORE

  5. 4. A Study on Fault Tolerance of Object Detector Implemented on FPGA

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Tiancheng Yang; [2023]
    Keywords : Object detection; YOLO-v3-tiny; Fault tolerance; FPGA; VHDL; Hardware accelerator; Triple-modular redundancy; Time redundancy; Stuck-at-faults;

    Abstract : Objektdetektering har fått stort forskningsintresse de senaste åren, eftersom det är maskiners ögon och är en grundläggande uppgift inom datorseende som syftar till att identifiera och lokalisera föremål av intresse. Hårdvaruacceleratorer syftar vanligtvis till att öka genomströmningen för realtidskrav samtidigt som energiförbrukningen sänks. READ MORE

  6. 5. Develop a Graphical User Interface for the assembler for SiLago Platform

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Yuxuan Wang; [2023]
    Keywords : Graphic intermediate representation; Graphical analytic system; High-level synthesis tool; Grafisk mellanrepresentationen; Grafiskt analytiskt system; Högnivå syntes verktyg;

    Abstract : Vesyla-II is developed as the High-Level Synthesis (HLS) tool serving the SiLago platform. The assembler Manas is a part of the Coarse Grain Reconfigurable Architectures (CGRA) compiler in Vesyla-II, which is used to transform the information from source code into the target language. READ MORE