Essays about: "SiLago"

Showing result 1 - 5 of 6 essays containing the word SiLago.

  1. 1. Rate Flexible Soft Decision Viterbi Decoder using SiLago

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Naveen Bantwal Baliga; [2021]
    Keywords : SiLago; Viterbi Decoder; Rate-flexible; Soft Decision; WLAN 802.11a; Strongly Connected Trellis; CGRA; Convolution Encoding; BER; SiLago; Viterbi-avkodare; hastighetsflexibel; mjukt beslut; WLAN 802.11a; starkt kopplade trellis; CGRA; konvolutionskodning; BER;

    Abstract : The IEEE 802.11a protocol is part of the IEEE 802 protocols for implementing WLAN Wi- Fi computer communications in various frequencies. These protocols find applications worldwide, covering a wide range of devices like mobile phones, computers, laptops, household appliances, etc. READ MORE

  3. 2. Global clock distribution in the SiLago platform

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Jordi Altayó; [2020]
    Keywords : ;

    Abstract : The extreme evolution of Very Large Scale Integration (VLSI) design has followed Moore’s law for the past decades, which predicts a doubling of the number of transistors that can be implemented on a chip every 18 months. However, tightly coupled with the evolution of the technology capabilities, the complexity during the implementation of such designs has also increased dramatically. READ MORE

  4. 3. Low Density Parity Check Encoder and Decoder on SiLago Coarse Grain Reconfigurable Architecture

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Weijiang Kong; [2019]
    Keywords : LDPC; CGRA; Reconfigurable architecture; VLSI design; ASIC; LDPC; CGRA; Konfigurerbar arkitektur; VLSI design; ASIC;

    Abstract : Low density parity check (LDPC) code is an error correction code that has been widely adopted as an optional error correcting operation in most of today’s communication protocols. Current design of ASIC or FPGA based LDPC accelerators can reach Gbit/s data rate. READ MORE

  5. 4. Implementation of 3GPP LTE QPP Interleaver for SiLago

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Spandan Dey; [2019]
    Keywords : Quadratic Permutation Polynomial; QPP; interleaver; SiLago; Address Generation Unit; AGU; 3GPP; LTE; turbo codes; parallel; Quadratic Permutation Polynomial; QPP; interleaver; SiLago; Address Generation Unit; AGU; 3GPP; LTE; turbo codes; parallel;

    Abstract : Modern wireless communication systems have seen an increased usage of various channel coding techniques to facilitate improved throughput and latency. Interleavers form an integral part of these coding techniques and play a critical role by making the communication more robust and resilient to noise and other interference. READ MORE

  6. 5. Characterization, Clock Tree Synthesis and Power Grid Dimensioning in SiLago Framework

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Rohit Prasad; [2019]
    Keywords : SiLago; clock tree; synthesis; power characterization; power grid; digital hardware design; physical design;

    Abstract : A hardware design methodology or platform is complete if it has the capabilities to successfully implement clock tree, predict the power consumption for cases like best and worst Parasitic Interconnect Corners (RC Corners), supply power to every standard cell, etc.This thesis has tried to solve the three unsolved engineering problems in SiLago design. READ MORE