Essays about: "shared memory system"

Showing result 16 - 20 of 67 essays containing the words shared memory system.

  1. 16. Load Balancing of Parallel Tasks using Memory Bandwidth Restrictions

    University essay from Mälardalens högskola/Akademin för innovation, design och teknik

    Author : Tommy Ernsund; Linus Sens Ingels; [2019]
    Keywords : parallel; load balancing; memory; bandwidth; bandwidth restrictions;

    Abstract : Shared resource contention is a significant problem in multi-core systems and can have a negative impact on the system. Memory contention occurs when the different cores in a processor access the same memory resource, resulting in a conflict. READ MORE

  3. 17. Extending Distributed Shared Memory with Transactional Memory Support

    University essay from Uppsala universitet/Institutionen för informationsteknologi

    Author : Sven Lundgren; [2019]
    Keywords : ;

    Abstract : Parallel programming has become increasingly important both as a programming skill and as a research topic over the last decades. Multicore computers and mobile devices are part of our daily lives, and computer clusters facilitate research in many areas all over the world. READ MORE

  4. 18. Modeling Shared Memory Access in a SystemC/TLM-based Many-core Virtual Platform

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Tony Lundgren; [2019]
    Keywords : ;

    Abstract : The market for embedded devices is fast paced and is growing quickly. To be competitive, time-to-market is important for new products. To shorten the time it takes to release new products, hardware simulators in the form of virtual platforms are developed to allow software development to start before hardware is available. READ MORE

  5. 19. Low Density Parity Check Encoder and Decoder on SiLago Coarse Grain Reconfigurable Architecture

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Weijiang Kong; [2019]
    Keywords : LDPC; CGRA; Reconfigurable architecture; VLSI design; ASIC; LDPC; CGRA; Konfigurerbar arkitektur; VLSI design; ASIC;

    Abstract : Low density parity check (LDPC) code is an error correction code that has been widely adopted as an optional error correcting operation in most of today’s communication protocols. Current design of ASIC or FPGA based LDPC accelerators can reach Gbit/s data rate. READ MORE

  6. 20. Extending Timing Analysis for Non­ Preemptive Task Sets on Multicore Under the AER Model

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Jacob Kimblad; [2019]
    Keywords : ;

    Abstract : Real-time multi-core systems with shared memory are harder to analyze due to varying execution times caused by congestion in accessing the shared memory. A promising way to make these systems more deterministic is the Acquisition-Execution-Restitution (AER)-model which takes a memory-centric approach to scheduling which enables the multicore problem to be seen as a single core scheduling problem. READ MORE