An Embedded Multi-Core Platform for Mixed-Criticality Systems : Study and Analysis of Virtualization Techniques

Abstract: The common availability of multiple processors in modern CPU devices and the need to reduce cost of embedded systems has created a drive for integrating functionalities from different parts of a system into a single Multi- Processor System-on-Chip (MPSoC) device. As a result, system resources are shared amongst the critical and non-critical components of the system, which results in a mixed-criticality system (MCS). An example of a MCS is to combine an airbag control unit with the infotainment system of a car, in such a case, both components must be certified unless an isolation mechanism that can prevent the non-critical to interfere with the critical subsystems is implemented. This isolation can be achieved via spatial and temporal partitioning of system resources, such as static mapping of CPUs to critical tasks, memory and IO virtualization, and time domain multiplexing of applications. System isolation is currently achievable through virtualization techniques, and is commonly used in data centers and personal computers. Recently, virtualization solutions have been emerging for embedded systems in order to cope with the increased design complexity, the stringent non-functional requirements, and to facilitate the certification process of MCS. The achieved performance, safety, security, and robustness in a virtualized system depends on the virtualization architecture and hardware platform. This thesis work performs state-of the art research in the field of mixedcriticality embedded systems with a focus on virtualization of embedded systems. As a result, a deep study of virtualization architectures, and open-source virtualization solutions is conducted in order to understand the consequences of using this technology in MCS. The work is concluded with a design and implementation of mixed-criticality embedded system that leverages the hardware capabilities of the target device (Zynq-7000 all programmable SoC), and contributes to the Living Lab WP7 of the EMC2 project.