Hybrid Quaternary/Binary Computing

Abstract: Due to scaling limitations and the end of Dennard scaling, energy efficiency has become a primary design goal. Approximate computing aims to solve this problem by sacrificing accuracy for efficiency. This project have evaluated a dual mode architecture that gives accuracy when needed and energy efficiency when it is possible. By combining binary and quaternary logic, up to half of the logic could be deactivated whenever absolute correctness is not critical. This project also proposes a hybrid mode, which aims to increase the number of cases where a more energy efficient representation could be used. By combining the two modes through using the more stable binary logic for the bits with higher significance, while at the same time using the energy efficient quaternary logic for the bits with the least significance, energy can still be saved while at the same time drastically limiting the potential size of the error. Simulations have shown that the hybrid mode not only succeeds in decreasing the maximum size of errors, but also reduces the total number of errors, compared to the quaternary mode. Results show increased energy efficiency of 10% without altering the perceived result at all. If we allow for some degradation of the result, the energy efficiency would improve with almost 40%.