Design and Implementation of AXI-based Network-on-Chip Systems for Flow Regulation

Abstract: In Network-on-Chip (NoC), controlling Quality-of-Service is crucial in order to build predictable systems. In this project, we design and implement an AXI-based system on the Nostrum NoC, which features a 2D mesh topology and deflective routing. The main components we add to the Nostrum NoC are master and slave interfaces. The master interface conducts packetization, queuing and multiplexing. The slave interface performs de-packetization, queuing, de-multiplexing and, in particular, reordering of transfers. We also build master and slave modules to serve as traffic generators and sinks. One particular feature of the master module is that it can regulate traffic burstiness while generating traffic. All these models are implemented in VHDL at the RTL. The interface protocol of masters and slaves is the AXI from ARM. With the above components, we designed experiments to show the effect of traffic regulation. Our results show that higher burstiness traffic results in larger transfer delay and bigger backlog. We can conclude that the transfer delay and backlog can be controlled to some degree in a best-effort network via regulating the traffic burstiness.