Power Supply Rejection (PSR) Enhancement Techniques for Fully Integrated Low-Dropout (LDO) Regulators

Abstract: In this present world, there is a huge requirement of portable devices for that the analysis of low-dropout or LDO regulators have been on high priority. So, for every respective device, there is a power budget that acts as the main constraint to design an LDO. The LDO design aims to suppress the noise and supply noise-free or low noise output. This thesis paper illustrates several designs of output capacitor-less LDO architecture to enhance Power Supply Rejection (PSR) and optimization of the ideas from different literature to achieve the low quiescent current, stability with fast transient response while the input voltage is low over a wide range of load current. Differ-ent types of transistor schematic designs under definite specifications of the LDOs, which are mostly integrated by major components like Error Amplifier (EA) and pass transistor, feedback resistors, and relatively small output capacitor have mostly considered for the designs. However, some buffer attenuation techniques which can improve the PSR have also been shown with a proper diagram. The design of LDOwith the components and how to design the pass device and their trade off’s have been has been discussed. Different techniques of PSR enhancement among which some of the techniques have been implemented have been illustrated with respective diagrams. A study of executed techniques under the specifications with comparative results has been shown with their trade-off with the other architecture. The contribution is an LDO that has been simulated in Cadence specter and designed in CMOS FinFET process node atVdd= 0.95 V with a load current of 50 mA -75 mA and an output voltage of 0.75 V with a small output capacitor of 200 pF, a PSR of−25 dB at 100 MHz has been achieved whereas the current consumption at the load is 245μA, while meeting the targeted stability analysis of gain margin and phase margin of 47 dB and 63◦respectively. A small voltage droop of 36. 6mV for rising edge and−15.99 mV for falling edge over a 100μA to 75 mA step-change in10 ns has been observed.