Hardware implementation of a Partial Dynamic Reconfiguration Controller

Abstract: Partial Dynamic Reconfiguration (PDR) of Field Programmable Gate Arrays (FPGAs) wasintroduced to overcome the need for more resources on the FPGA fabric. This enabled parts of thedevice to be reconfigured at runtime, while the rest of the system continued to function without anyinterruptions. Therefore, PDR could change the functionality and efficiency of the system in order toaccommodate more hardware modules, save power and fabric area. Typically, PDR involves the designof modules that are independent of each other so that they can be loaded on the same fabric area(reconfigurable region) one after the other. This thesis will introduce a framework that enables designers to use PDR in their applications,without having to go into the details of the reconfiguration process. It provides an elegant interface,based on standalone IP modules and an API, which can be used to load modules on to the FPGA fabricat runtime with very little overhead to the main processor. The framework will copy the partial bitfiles from the configuration memory and reconfigure the FPGA while the application continues toexecute useful computations. It will notify the application with an interrupt after completion of thereconfiguration process so that the application can switch context between hardware and softwaremodules. We validate our controller by using simple test cases that perform FPGA configurationprefetching. However, the framework presented in this thesis can be used as a foundation for manysystem optimizations targeted at dynamically reconfigurable platforms.