A digital integer-N PLL architecture using a pulse-shrinking TDC for mmWave applications.

Abstract: With the move of the broadband cellular network towards 5G taking off and the preparatory work on 6G and beyond starting, the need for low-complexity, low-power, and high-performance frequency synthesis using Phase-Locked Loop (PLL)s increases. As we get deeper into the mm-wave frequencies and push towards frequencies in the order of 50-70 GHz design challenges with existing PLL architectures, such as limited technology scaling and limited in-band noise performance become more apparent. Other designs have tried overcoming these problems, for example by using single-bit phase detection at the cost of increased complexity when trying to control the bandwidth, or designing the loop with lower bandwidth to suppress in-band noise at the cost of requiring a lower noise and thus more power hungry oscillator. This thesis proposes a new Phase-locked loop architecture implemented in a 22nm node to combat these issues, utilizing a Pulse-Shrinking Time-To-Digital Converter (PS-TDC) offering sub-pico-second resolution with minimal power consumption in lock. The results found in this thesis have shown the viability of such a design, offering good in-band performance, allowing for wide bandwidth, and the use of a cheaper low-power Digital-Controlled Oscillator (DCO). The PS-TDC architecture combined with control logic implemented in this project can drastically decrease power consumption in lock while being able to compensate for process variations to optimize jitter performance. Additionally, by utilizing a Phase-Frequency Detector (PFD) and gear-shifting logic it has been shown that robust and fast locking can be achieved.