Automatic Generation of Real-Time Machine Learning Architectures

Abstract: An era is rising where more embedded systems are being moved to the edge. Everything from automated vehicles to smartphones with more complex machine learning architectures needs to be provided. Hence, the requirements of contributing with efficiency emerge more. Not only is this required for offline applications, but the demand is also rising for real-time applications. Therefore, software developers that are experts in real-time machine learning architecture may be in a situation where this architecture needs to be implemented on an embedded system that can provide the efficiency that is being demanded.FPGAs can provide with these demands. However, it is time-consuming to implement hardware description language (HDL) if not an expert. Our project has a main focus on building a frontend tool that gen-erates a dataflow programming language called CAL from a cus-tomized implementation for a specific machine learning model. The dataflow programming language CAL is used to accomplish an ef-ficient generation of hardware circuits. In this project, our primary focus is latency.The execution time of a software implementation has been compared to a hardware implementation where a Raspberry Pi 3b has con-tributed with the software implementation. A design space explo-ration has been done where different designs from the same model have been analyzed. In addition, the modules have also been ana-lyzed separately. In the analysis, latency is the factor explored.Results present a much faster execution time on the hardware im-plementation than the software implementation. Final results demon-strate a lower overall delay for modules implemented in parallel over modules implemented in serial. A parallel implementation reduced the overall delay with 242%.