Essays about: "Verification Intellectual Property"
Showing result 1 - 5 of 7 essays containing the words Verification Intellectual Property.
-
1. Novel Method of ASIC interface IP development using HLS
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. READ MORE
-
2. Modularity, Scalability, Reusability, Configurability, and Interoperability of ASIC/FPGA Verification IP
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : The complexity of chip design has been exponentially rising, resulting in increased complexity and costs in chip verification. This rise in complexity results in increased time to market and increases risks of chip in fabrication, that can be catastrophic and result in major losses. READ MORE
-
3. Configurable, scalable single-ended sense amplifier with additional auxiliary blocks for low-power two-port memories in advanced FinFET technologies
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : System on Chip (SoC) designs contain a variety of Intellectual Property (IP) cores, including digital signal processing blocks, media and graphics processing units, as well as processing core units that employ multiple-port memories to enhance performance and bandwidth. These memories allow parallel read/write operations from the same memory blocks from different ports. READ MORE
-
4. Energy efficient Ericsson Many-Core Architecture (EMCA) IP blocks for 5G ASIC
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : Power consumption has become a leading concern for SoC aimed at 5G products that demand increased functionality, smaller form factors, and low energy footprint. For some EMCA IP blocks a hierarchical clock gating mechanism ensures coarse-grained power savings based on actual processing need but for many blocks this approach cannot be employed. READ MORE
-
5. Development of a new verification environment for a GPU hardware block using the Universal Verification Methodology
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : The invention of the integrated circuit is a key milestone in the history of electronic circuits. Since its introduction the number of components on a chip have increased rapidly, making them more powerful and able to perform complex operations, but it has also changed the design process. READ MORE
