Essays about: "digital hardware synthesis"

Showing result 1 - 5 of 16 essays containing the words digital hardware synthesis.

  1. 1. Novel Method of ASIC interface IP development using HLS

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Anestis Athanasiadis; Chandranshu Mishra; [2023]
    Keywords : High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

    Abstract : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. READ MORE

  3. 2. Circuit design and hardware implementation of an analog synthesizer

    University essay from Uppsala universitet/Institutionen för materialvetenskap

    Author : Olle Murhed; [2023]
    Keywords : synthesizer; analogue; circuit design; sound; sound synthesis; oscillator; VCO; filter; amplifier; sequencer; control voltage; breadboard;

    Abstract : Since the heyday of analogue synthesizers in the 70's, they have largely been replaced by digital hardware and software synthesizers. However, in recent years, there has been a revival in analogue designs, possibly due to its ``warmer" sound. READ MORE

  4. 3. FPGA Accelerated Digital Image Correlation For Clamping Force Measurement

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : János Csanád Csuvarszki; [2023]
    Keywords : Digital image correlation; Field-programmable gate array; High-level synthesis;

    Abstract : Digital image correlation is a contactless optical method used for displacement and strain measurement which has become increasingly popular in the field of experimental mechanics. A specialized use case for the algorithm is to measure the clamping force in bolted joints, a crucial metric when considering the longevity and reliability of the constructs. READ MORE

  5. 4. Design a Three-Stage Pipelined RISC-V Processor Using SystemVerilog

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Ziyan He; [2022]
    Keywords : RISC; RISC-V; ISA; SystemVerilog; RTL simulation; RV32IM; CPI; RISC; RISC-V; ISA; SystemVerilog; RTL simulering; RV32IM; CPI;

    Abstract : RISC-V is growing in popularity as a free and open RISC Instruction Set Architecture (ISA) in academia and research. Also, the openness, simplicity, extensibility, and modularity, among its advantages, make it more and more used by designers in industry. The aim of this thesis is to design an open-source RISC-V processor. READ MORE

  6. 5. FPGA Implementation of the ORB Algorithm

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Xinyuan Zhang; Emil Sturk Sellstedt; [2022]
    Keywords : Technology and Engineering;

    Abstract : Image feature extraction has become a key technology in the field of autonomous Artificial Intelligence. The algorithm Oriented FAST and Rotated BRIEF (ORB), uses established technologies in image processing to allow a computer to ”see” and navigate its surroundings. READ MORE