Essays about: "Code Synthesis"
Showing result 1 - 5 of 50 essays containing the words Code Synthesis.
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1. Difference Between Memory-based Storage and Register-based Storage on FPGAs
University essay from Linköpings universitet/Institutionen för systemteknikAbstract : Memory-based storage and register-based storage are commonly used storagetypes in fpgas. This thesis aims to build up the architecture of memory-basedstorage and register-based storage, implement the corresponding methods, compare the difference between them and determine which kind of storage workswell under different circumstances. READ MORE
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2. Code Synthesis for Heterogeneous Platforms
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Heterogeneous platforms, systems with both general-purpose processors and task-specific hardware, are largely used in industry to increase efficiency, but the heterogeneity also increases the difficulty of design and verification. We often need to wait for the completion of all the modules to know whether the functionality of the design is correct or not, which can cause costly and tedious design iteration cycles. READ MORE
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3. Improving the Synthesis of Annotations for Partially Automated Deductive Verification
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : This work investigates possible improvements to an existing annotation inference tool. The tool is part of a toolchain that aims to automate the process of software verification using formal methods. READ MORE
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4. Develop a Graphical User Interface for the assembler for SiLago Platform
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Vesyla-II is developed as the High-Level Synthesis (HLS) tool serving the SiLago platform. The assembler Manas is a part of the Coarse Grain Reconfigurable Architectures (CGRA) compiler in Vesyla-II, which is used to transform the information from source code into the target language. READ MORE
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5. High Level Synthesis for ASIC and FPGA
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : This thesis aims to evaluate the performance of Siemens’ High Level Synthesis (HLS) tool Catapult. HLS can be considered the next step up in abstraction level from writing traditional Register Transfer Level (RTL) code which is time consuming and error prone. READ MORE