Code Synthesis for Heterogeneous Platforms

Abstract: Heterogeneous platforms, systems with both general-purpose processors and task-specific hardware, are largely used in industry to increase efficiency, but the heterogeneity also increases the difficulty of design and verification. We often need to wait for the completion of all the modules to know whether the functionality of the design is correct or not, which can cause costly and tedious design iteration cycles. Correctness by construction is a methodology that proposes tackling this problem by separating specification and implementation and bridging them through formal methods. Code synthesis is one of these methods which refers to the process of generating low-level codes implementing the desired system from high-level modelling languages. Formulating a generic synthesis method can, in principle, decrease error rates and shorten development cycles since target-specific usage and mechanisms can be systematically taken care of in an automatic manner, whereas the designer needs only to ensure the functional correctness of the high-level specification model. In this respect, this thesis aims to use the open-source Zero Overhead Topology Infrastructure (ZOTI) methodology to formulate a synthesis process from a denotational graph-based representation of an application, tailored towards heterogeneous hardware/software implementations. The case study presents the partially automated synthesis of an open-source streaming processing subsystem on a Xilinx Zynq-based system-on-chip architecture consisting of a software part and a custom hardware accelerator part, where both C software and VHDL hardware are generated from the input model. While the initial results demonstrate a promising path for systemizing the code generation process, certain aspects of the synthesis, such as generating glue code for complex data types (e.g., multi-arrays), are left out of the scope of this thesis and will be explored in future work.