Investigation of high performance configurations on the Evolved Packet Gateway
Abstract: Modern servers today are based on multi-socket motherboards to increase their powerand performance figures. These setups provide CPU interconnection through a highspeed bus. If processes on one CPU need access to memory or devices local to anotherCPU, they need to traverse this bus and this adds a delay to the execution time. Thisis where the concept of Non-Uniform Memory Access (NUMA) presents as a solution.Every socket with its local memory is considered a node, that is locked and processesare not allowed to migrate. This means that loading instructions has low latency, butthey can also access the main memory connected to the other NUMA nodes at a givenpenalty cost. The latest CPUs such as the EPYC series from AMD are using this concepteven within the processor module, and there is no possibility to avoid taking into accountNUMA aspects.There has been a plethora of benchmarks to analyze the impact of NUMA node architectureon different processors. In this work, we have used the Packet Gateway of theEvolved Packet Core (EPC) as a test case to investigate the effectiveness of NUMA architectureon Intel processors on a virtual large-scale distributed production system withhigh performance requirements. On the virtualization setups, di erent CPU pining anddeployment strategies are used, while Packet Per Second (pps) is the preferred performanceindicator in systems like the Evolved Packet Gateway (EPG).We further describeand analyze different scenarios, combining CPU pinning and process placement, withinthe virtual machines running the EPG.
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