Test Generation For Digital Circuits – A Mapping Study On VHDL, Verilog and SystemVerilog

University essay from Mälardalens högskola/Inbyggda system

Author: Ashish Alape Vivekananda; [2018]

Keywords: ;

Abstract: Researchers have proposed different methods for testing digital logic circuits. The need for testing digital logic circuits has become more important than ever due to the growing complexity of such systems. During the development process, testing is focusing on design defects as well as manufacturing and wear out type of defects. Failures in digital systems could be caused by design errors, the use of inherently probabilistic devices, and manufacturing variability. The research in this area has focused also on the design of digital logic circuit for achieving better testability. In addition, automated test generation has been used to create tests that can quickly and accurately identify faulty components. Examples of such methods are the Ad Hoc techniques, Scan Path Technique for testable sequential circuits, and the random scan technique. With the research domain becoming more mature and the number of related studies increasing, it is essential to systematically identify, analyse and classify the papers in this area. The systematic mapping study of testing digital circuits performed in this thesis aims at providing an overview of the research trends in this domain and empirical evidence. In order to restrict the scope of the mapping study we only focus on some of the most widely-used and well-supported hardware description languages (HDLs): Verilog, SystemVerilog and VHDL. Our results suggest that most of the methods proposed for test generation of digital circuits are focused on the behavioral level and Register Transfer Levels. Fault independent test generation is the most frequently applied test goal and simulation is the most common experimental test evaluation method. Majority of papers published in this area are conference papers and the publication trend shows a growing interest in this area. 63% of papers execute the test method proposed. An equal percentage of papers experimetnatlly evaluate the test method they propose. From the mapping study we inferred that papers that execute the test method proposed, evaluate them as well.

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