Next Generation SDN Switches Using Programming Protocol-Independent Packet Processors

Abstract: Over recent years, Software Defined Networking has enabled operators to control the network and realize new networking topologies. With increasing network traffic and protocol formats that aim at managing the traffic efficiently, the capabilities offered by Software Defined Networking alone are currently limited by the underlying fixed hardware infrastructure. The inflexibility involved in redesigning the hardware forces the bottom-up approach defined by switch vendors in describing the network and limits the capabilities offered to operators for further innovation. To meet the demands of ensuring a higher degree of flexibility to design, test and guarantee a faster time to market, the concept of Softly Defined Networks was introduced. The idea in addition to offering the conventional advantages of Software Defined Networking is based upon implementing a re-programmable data-plane. Field-Programmable Gate Arrays offered a higher degree of flexibility and capability to handle such designs. Programming Protocol-independent Packet Processors(P4) is a high-level language continuously evolving to define data-planes for various networking devices. The aim of P4 is for network operators to customize the underlying hardware with minimum constraints and ease, independent of the target. Therefore, the three major goals while defining such a language revolved around reconfigurability of hardware after being deployed, protocol independence to permit customization without constraints and target independence for users to be less concerned of the underlying hardware. Recent advances in P4 with the added support in terms of compatible targets and compilers have made P4 a viable opportunity to realize a re-programmable hardware. This work contributes towards exploring the ease of incorporating the capabilities of P4 in realizing a flexible data-plane. To achieve the same and study its characteristics a supporting two lane hardware pipeline is proposed that is capable of accommodating P4 upon a Kintex 7 FPGA. Primarily, a custom P4 module is defined that is capable of performing L2 operations upon a double tagged Ethernet frame using an appropriate architecture model. Subsequently, to integrate the P4 description on hardware the proposed supporting pipeline is implemented at a line rate of 10Gbps using the essential building blocks that help in observing the desired processing. Using a test setup, the design shall be further tested for the expected data-plane activity based upon the populated match-action rules. In terms of resource utilization, the overall design consumes less than 15% of the available resources and incurs an average latency of 5.71us. In addition to the ease of customization compared to the conventional fixed data-plane descriptions, it is vital to analyze the cost inherited while adopting P4. The final design is therefore studied in terms of resource utilization and latency by increasing the complexity of the P4 definition with regard to the number of headers, tables and write operations(H-T-W) for the adopted compiler. In the case of eight headers, tables and write operations(8H-8T-8W), there is an average latency of 8.01us and the P4 description alone demands 51536 LUTs, 77789 FFs and 118.5 BRAMs in terms of resource utilization. Finally, the article discusses the extent to which the proposed top-down approach is implemented and is capable of redefining the network as we know it.