Implementation of a VBR MPEG-stream receiver in an FPGA

Abstract: Nowdays, the transmission of digital TV-signals tends to move towards more untraditional medias, such as TCP/IP networks. This thesis focused on the problems involved in receiving MPEG transport streams of variable bitrate from a TCP/IP connection, such as jitter and clock synchronization. A suggestion for recovering the transport stream is presented along with a implementation for an Xilinx FPGA targeted for a head end device. The implementation was written in a mix of VHDL and Verilog.